Title :
Compact modeling of gate sidewall capacitance of DG-MOSFET
Author :
Roy, Ananda S. ; Enz, Christian C. ; Sallese, J.M.
Author_Institution :
Electron. Lab., Ecole Polytech. Fed. de Lausanne
Abstract :
Recent studies show that the gate sidewall capacitance of an underlap double gate device plays an important role in the design and optimization of the device. To date, only semiempirical techniques are used to model this important capacitance. In this brief, the authors present an analytical model of the fringe capacitance and find out a geometry dependent quantity which determines the scaling of this capacitance
Keywords :
MOSFET; capacitance; semiconductor device models; DG-MOSFET; analytical model; compact modeling; double gate device; fringe capacitance; gate sidewall capacitance; geometry dependent quantity; Analytical models; Conformal mapping; Delay effects; Design optimization; Geometry; Laboratories; MOSFET circuits; Nanoscale devices; Parasitic capacitance; Solid modeling; Conformal mapping; double gate MOSFET; fringecapacitance; gate underlap;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.882029
