40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW

Author

Galdi, Ivano ; Bonizzoni, Edoardo ; Malcovati, Piero ; Manganaro, Gabriele ; Maloberti, Franco

Author_Institution

Dept. of Electron., Univ. of Pavia, Pavia

Volume

43

Issue

7

fYear

2008

fDate

7/1/2008 12:00:00 AM

Firstpage

1648

Lastpage

1656

Abstract

A bandpass modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 . The power consumption is 16 mW with 1.8 V supply.

Keywords

CMOS integrated circuits; sigma-delta modulation; CMOS technology; bandpass modulator; bandwidth 1 MHz; cross-coupled paths; frequency 40 MHz; power 16 mW; second-order modulators; sigma-delta modulator; time-interleaved modulators; voltage 1.8 V; Bandwidth; CMOS technology; Clocks; Dynamic range; Energy consumption; Filtering theory; Frequency; Sampling methods; Signal synthesis; Transfer functions; Analog–digital conversion; CMOS integrated circuits; sigma-delta modulation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.923728

Filename

4550636