Title :
A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS
Author :
Pellerano, Stefano ; Palaskas, Yorgos ; Soumyanath, Krishnamurthy
Author_Institution :
Commun. Circuits Lab., Intel Corp., Hillsboro, OR
fDate :
7/1/2008 12:00:00 AM
Abstract :
This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for ldquocorrect-by-constructionrdquo design at mm-wave frequencies and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with a NF of 6.5 dB, while drawing 26mA per stage from 1.65 V. Output is 3.8 dBm. At , each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB, respectively. Measured results are in excellent agreement with simulations, proving the effectiveness of the proposed design methodology. A custom set-up for mm-wave NF measurement is also extensively described in the paper.
Keywords :
CMOS integrated circuits; low noise amplifiers; millimetre wave amplifiers; CMOS integrated circuit; RC parasitic extraction; correct-by-construction design; dual-stage cascode LNA; electromagnetic simulations; first-pass silicon success; frequency 64 GHz; gain 15.5 dB; integrated LNA; low naoise amplifier; millimeter wave amplifier; noise figure 6.5 dB; size 90 nm; CMOS technology; Electromagnetic devices; Electromagnetic measurements; Electromagnetic modeling; Frequency measurement; Gain; Millimeter wave measurements; Millimeter wave technology; Noise measurement; Semiconductor device modeling; CMOS integrated circuits; electromagnetic analysis; impedance matching; millimeter-wave amplifiers; millimeter-wave measurements; noise measurement; transmission lines;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.922395