A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD

This paper presents a highly power-efficient stereo delta-sigma ADC designed for high-precision applications, with measured inter-channel isolation over 130 dB. This design adopts a single-loop, fifth-order, 33 level analog modulator with positive and negative feedforward paths. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer. These new techniques suppress signal dependent energy inside the delta-sigma loop, reduce internal channel coupling and power consumption. Manufactured in 0.35 mum double poly, three metal CMOS process, the single-die chip includes two analog modulators, on-chip bandgap reference circuit, decimation filter and serial interface circuits. The core die area is around 14.8 mm². The ADC achieves 124 dB dynamic range (A-weighted), -111 dB THD over 20 kHz bandwidth. Total power consumption is less than 330 mW.