Field 24 amended in b/hAnalysis of mismatch sensitivity in a simulataneously latched CMOS sense amplifier

Author

Sarpeshkar, Rahul ; Wyatt, John L., Jr. ; Lu, Nicky C. ; Gerber, Porter D.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

Volume

39

Issue

5

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

277

Lastpage

292

Abstract

A new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in DRAMs, to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bitline load capacitance mismatch is derived. The mathematical methods used in the derivation of the formula are described in detail. The formula yields insight on the DRAM sensing operation. The perturbation approach used is novel and rigorous and yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design

Keywords

CMOS integrated circuits; DRAM chips; amplifiers; sensitivity analysis; CMOS sense amplifier; DRAMs; bitline load capacitance mismatch; mismatch sensitivity; parasitic capacitance mismatch; threshold voltage mismatch; transconductance mismatch; vertically matched; Closed-form solution; Differential amplifiers; Fabrication; MOS devices; Optimal control; Parasitic capacitance; Random access memory; Signal restoration; Threshold voltage; Transconductance;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.142029

Filename

142029