Field 24 amended in b/hAnalysis of mismatch sensitivity in a simulataneously latched CMOS sense amplifier

A new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in DRAMs, to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bitline load capacitance mismatch is derived. The mathematical methods used in the derivation of the formula are described in detail. The formula yields insight on the DRAM sensing operation. The perturbation approach used is novel and rigorous and yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design