Title :
An optimized 1.0-μm CMOS technology for next-generation channelless gate arrays
Author :
Ushiku, Yoshitaka ; Kobayashi, Takehiko ; Yoshida, Atsushi ; Itoh, N. ; Nishiyama, A. ; Nakata, Rempei
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
4/1/1988 12:00:00 AM
Abstract :
An optimized 5-V 1.0-μm CMOS technology has been developed to achieve high speed and high packing density for channelless gate arrays. In addition to the downward scaling of CMOS device geometry, reduction of the parasitic resistances is essential for next-generation channelless gate arrays. The technology utilizes sidewalled PMOS and lightly doped drain (LDD) NMOS structures with 1.0-μm actual physical gate lengths and 20-nm gate-oxide thickness. Tungsten metal is selectively deposited on the source and drain regions to reduce sheet resistivity, thus gaining extra speed improvement. This technology was applied to a large-scale gate array of over 40 K usable gates; high-speed (290-ps) operation has been achieved for a two-input NAND gate with a fan-out of 2. An advanced graphic processor with over 35 K used gates has been successfully demonstrated
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; digital integrated circuits; integrated circuit technology; metallisation; tungsten; 1 micron; 20 nm; 290 ps; 5 V; ASIC; CMOS technology; LDD; NMOS structures; VLSI; W metallisation; custom ICs; fan-out; gate lengths; gate-oxide thickness; graphic processor; high packing density; high speed; large-scale gate array; lightly doped drain; next-generation channelless gate arrays; parasitic resistances; scaling; sea of gates; sidewalled PMOS; speed improvement; two-input NAND gate; Application specific integrated circuits; CMOS technology; Conductivity; Etching; Geometry; Graphics; Implants; Isolation technology; Large-scale systems; MOS devices; Macrocell networks; Tungsten; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
