DocumentCode :
773911
Title :
The analysis of digital integrators for test response compaction
Author :
Rajski, Janusz ; Tyszer, Jerzy
Author_Institution :
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
Volume :
39
Issue :
5
fYear :
1992
fDate :
5/1/1992 12:00:00 AM
Firstpage :
293
Lastpage :
301
Abstract :
The compaction properties of integrators that could be used in the built-in self-test (BIST) environment instead of linear finite-state-machine-based comparators are studied. Markov chain models are used to provide a quantitative characterization of the compaction scheme in terms of its steady-state behavior as well as its transient properties. It is demonstrated that the asymptotic fault coverage drop depends on the fault injection site, the fault injection probability, and the gain factor. A simple modification of the standard integrator is also proposed in order to improve the quality of compaction. The proposed scheme introduces very small hardware overhead. It is compatible with the width of the data path, and the test can be applied at the normal mode speed
Keywords :
Markov processes; automatic testing; built-in self test; fault location; integrating circuits; logic circuits; logic testing; probability; BIST; Markov chain models; asymptotic fault coverage; built-in self-test; digital integrators; fault injection probability; fault injection site; gain factor; steady-state behavior; test response compaction; transient properties; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Digital signal processing; Digital signal processing chips; Hardware; Microelectronics; Signal processing algorithms;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.142030
Filename :
142030
Link To Document :
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