Title :
50 Gbit/s low-jitter dynamic decision circuit using Cbc compensation and semi-feed forward techniques
Author :
Nosaka, H. ; Ishii, K. ; Nakajima, H. ; Ida, M. ; Enoki, T. ; Shibata, T.
Author_Institution :
NTT Photonics Labs., NTT Corp., Kanagawa, Japan
Abstract :
A new low-jitter dynamic decision circuit is designed and fabricated using InP/InGaAs HBTs. Cbc compensation transistors and semi-feed forward loads are adopted to eliminate waveform distortion and residual double trace, respectively. A fabricated decision IC achieves error-free operation and wide eye opening for 50 Gbit/s 231-1 PRBS with 0.68 W power dissipation. Its RMS and peak-to-peak jitter of output data are 0.59 and 4.1 ps, respectively.
Keywords :
III-V semiconductors; bipolar digital integrated circuits; compensation; decision circuits; feedforward; gallium arsenide; heterojunction bipolar transistors; indium compounds; timing jitter; 0.68 W; 50 Gbit/s; Cbc compensation transistor; InP-InGaAs; InP/InGaAs HBT IC; double trace; dynamic decision circuit; eye quality; high-speed digital circuit; power dissipation; semi-feed forward load; timing jitter; waveform distortion;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030770
