DocumentCode :
774132
Title :
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing
Author :
Gregg, Justin ; Chen, Tom W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO
Volume :
15
Issue :
3
fYear :
2007
fDate :
3/1/2007 12:00:00 AM
Firstpage :
366
Lastpage :
376
Abstract :
The economics of continued scaling of silicon process technologies beyond the 90-nm node will face significant challenges due to variability. The increasing relative magnitude of within die process variations will cause power-frequency distributions to widen, thus, reducing manufacturing yields. Mitigating the effects of these process variations can be done by using the proposed individual well-adaptive body biasing (IWABB) scheme of locally generated body biases. IWABB allows for highly localized circuit optimizations with very little overhead in silicon area and routing resources. We present two algorithms to find near-optimal configurations of these biases which can be applied as postsilicon tuning. The proposed IWABB scheme can improve an initial yield from 12% to 73%
Keywords :
VLSI; integrated circuit design; integrated circuit yield; 90 nm; VLSI; individual well-adaptive body biasing; integrated circuit manufacture; integrated circuit yield; performance optimization; power optimization; Circuit optimization; Frequency; Integrated circuit manufacture; Manufacturing processes; Power generation economics; Routing; Semiconductor device manufacture; Silicon; Testing; Voltage; Design centering; VLSI; design for manufacturing; design for testability; genetic algorithms; integrated circuit design; integrated circuit manufacture;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2007.893626
Filename :
4154772
Link To Document :
بازگشت