Design and hardware architectures for dynamic Huffman coding

To date, dynamic Huffman coding has not been available for high-speed applications because the tree updating spends a lot of time by current adaptive Huffman coding hardware. The authors present concurrent techniques and the parallel hardware architectures for dynamic Huffman encoding and decoding. For step reduction, they employ the concurrent algorithm for encoding as well as proposing the frequency presetting approach for decoding. For hardware architecture, they use the content addressable memory for performing the massive searching operations in parallel. The output rate achieved by the proposed encoding architecture is near 1 bit/cycle and the input rate of our decoding architecture is from 0.6 to near 1 bit/cycle. Compared with the fast design which achieves the input/output rate of [log N]/[N+1] bit/cycle for an N-symbol source on average, our architectures apparently have higher throughput. Due to the improvement on the throughput, our dynamic coding architectures are able to serve for the applications with a higher speed demand