• DocumentCode
    774313
  • Title

    Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation

  • Author

    Meher, Pramod Kumar

  • Author_Institution
    Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore
  • Volume
    16
  • Issue
    9
  • fYear
    2006
  • Firstpage
    1041
  • Lastpage
    1050
  • Abstract
    A reduced-complexity convolutional formulation is presented for systolic implementation of the discrete cosine transform, where N-point transform can be computed by four numbers of nearly (N/4)-point circular-convolution-like operations. The proposed algorithm not only provides a reduction of computational complexity by four times over the conventional formulation, where N-point transform is computed via (N-1)-point cyclic convolution, but also leads to concurrent pipelined execution in linear systolic arrays. It is shown that the multiplications in the processing elements can be implemented by lookup-tables using dual-port ROM. Two variants of systolic structures using ROM-based multipliers are presented for efficient implementation of the proposed algorithm. The proposed structures are found to offer significant saving of hardware, require less latency, and yield more throughput over the existing structures. Apart from simplicity and regularity, the proposed structures would also have flexibility of implementation by CORDIC circuits and canonical-signed-digit-based multipliers as well
  • Keywords
    computational complexity; convolution; digital arithmetic; digital signal processing chips; discrete cosine transforms; read-only storage; systolic arrays; table lookup; (N-1)-point cyclic convolution; (N/4)-point circular-convolution-like operations; CORDIC circuits; DCT; N-point transform; ROM-based multipliers; TV-point transform; canonical-signed-digit-based multipliers; computational complexity; concurrent pipelined execution; discrete cosine transform; dual-port ROM; linear systolic arrays; low-complexity concurrent convolutional formulation; systolic designs; Computational complexity; Concurrent computing; Convolution; Delay; Discrete cosine transforms; Discrete transforms; Hardware; Read only memory; Systolic arrays; Throughput; Digital signal processing chip; discrete cosine transform (DCT); systolic array; very large-scale integration (VLSI);
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems for Video Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1051-8215
  • Type

    jour

  • DOI
    10.1109/TCSVT.2006.880191
  • Filename
    1705477