DocumentCode
774352
Title
Reconfigurable parallel VLSI processor for dynamic control of intelligent robots
Author
Fujioka, Y. ; Kameyama, M. ; Tomabechi, N.
Author_Institution
Fac. of Eng., Hachinohe Inst. of Technol., Japan
Volume
143
Issue
1
fYear
1996
fDate
1/1/1996 12:00:00 AM
Firstpage
23
Lastpage
29
Abstract
In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions. To reduce the delay time for multi-operand multiply additions, the architecture of the reconfigurable parallel processor is proposed. In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders. By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle. Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced. In addition, the utilised ratio of the multipliers and the adders is increased. The chip evaluation based on 0.8 μm CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 μs which is about 7.7 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs)
Keywords
intelligent control; parallel architectures; reconfigurable architectures; robots; chip evaluation; dynamic control; intelligent robots; parallel VLSI processor; reconfigurable parallel processor; sensor feedback control;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19960103
Filename
487921
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