DocumentCode
774389
Title
Linear-testable and C-testable N×Ny modified Booth multipliers
Author
Gizopoulos, D. ; Paschalis, A. ; Nikolos, D. ; Halatsis, C.
Author_Institution
Inst. of Inf. & Telecom, NCSR Demokritos, Athens, Greece
Volume
143
Issue
1
fYear
1996
fDate
1/1/1996 12:00:00 AM
Firstpage
44
Lastpage
48
Abstract
The testability of modified Booth multipliers is examined with respect to the cell fault model, an implementation-independent fault model. This is especially useful in design environments where the cell realisations are unknown. First, a linear-testable multiplier is proposed which can be tested with 2Nx+[Ny/2]+40 test vectors and requires only primary input, Zero delay negligible hardware overhead is imposed. Then, a C-testable multiplier is proposed which can be tested with 70 test vectors and requires only two extra primary inputs. Both the hardware and delay overheads are very small and decrease rapidly with increasing Nx or Ny. The linear-testable design is superior to the C-testable one, for small multipliers since it requires less test vectors in addition to the much smaller hardware overhead and zero delay overhead it imposes. For larger multipliers there is a trade-off between the number of test vectors, which is smaller for the C-testable design, and the overheads, which are smaller for the linear-testable design
Keywords
VLSI; digital arithmetic; integrated circuit testing; logic testing; C-testable design; cell fault model; implementation-independent fault model; linear-testable multiplier; modified Booth multipliers; test vectors; testability;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19960008
Filename
487924
Link To Document