• DocumentCode
    774512
  • Title

    Analysis and modelling of parasitic substrate coupling in CMOS circuits

  • Author

    Aragonés, X. ; Moll, F. ; Roca, M. ; Rubio, A.

  • Author_Institution
    Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
  • Volume
    142
  • Issue
    5
  • fYear
    1995
  • fDate
    10/1/1995 12:00:00 AM
  • Firstpage
    307
  • Lastpage
    312
  • Abstract
    Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed
  • Keywords
    CMOS integrated circuits; capacitance; integrated circuit modelling; integrated circuit noise; substrates; CMOS circuits; IC modelling; IC scaling; RAM cell; circuit-level model; device-level simulator; integrated circuits; noise coupling; parasitic substrate coupling; permanent errors;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2409
  • Type

    jour

  • DOI
    10.1049/ip-cds:19952164
  • Filename
    487937
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=774512