DocumentCode
774590
Title
Realisation of morphological operations
Author
Chen, C.H. ; Yang, D.-L.
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
142
Issue
6
fYear
1995
fDate
12/1/1995 12:00:00 AM
Firstpage
364
Lastpage
368
Abstract
Multi-input min and max operators are two essential components for dilation and erosion, which are two basic building units for morphological filtering. Many of the more complicated operations of morphological filtering can be decomposed by them. The min or max operator cascades after a bit-serial adder or subtractor is equal to a dilation or erosion operator. In the paper, an efficient algorithm and its implementation architecture for the min/max operation are proposed. The proposed algorithm and architecture can process bit by bit directly for all input signals without using threshold decomposition which requires more complicated hardware design. Any shape and size of the filtering window or structuring element can be realised. For a fixed window size, the shape of window is programmable by changing some input initial conditions. The computation time is independent of, and the hardware complexity is linear to, the window size. This implies that a very high throughput rate can be attained after an initial latency period required to fill up the pipeline. The proposed architecture is modular, regular and of local interconnections; and therefore amenable for VLSI implementation
Keywords
VLSI; adders; computational complexity; digital filters; filtering theory; mathematical morphology; VLSI implementation; bit-serial adder; computation time; dilation; erosion; filtering window; fixed window size; latency period; morphological filtering; morphological operations; multi-input max operators; multi-input min operators; structuring element;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:19952204
Filename
487945
Link To Document