DocumentCode
774818
Title
Issues in the design of a logic simulator: element modelling for efficiency
Author
Brown, A.D. ; Nichols, K.G. ; Zwolinski, M.
Author_Institution
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Volume
143
Issue
1
fYear
1996
fDate
2/1/1996 12:00:00 AM
Firstpage
21
Lastpage
27
Abstract
A unique method of using inertial cancellation in the detection of set-up and hold-time violations in flip-flops and other memory-like elements is described, together with an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques
Keywords
digital simulation; fault diagnosis; flip-flops; integrated memory circuits; logic design; efficiency; element modelling; flip-flops; hold-time violations; inertial cancellation; logic simulator; memory-like elements; queues; test circuit; timing violations;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:19960013
Filename
487969
Link To Document