Designing efficient parallel algorithms on CRAP

Author

Kao, Tzong-Wann ; Shi-Jinn Horng ; Wang, Yue-Li ; Tsai, Horng-Ren

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan

Volume

6

Issue

5

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

554

Lastpage

560

Abstract

A cross-bridge reconfigurable array of processors is a parallel processing system which has the ability to change dynamically the supported interconnection scheme during the execution of an algorithm. Based on this architecture, several O(1) time basic operations such as the transpose, the untranspose, the shift, the unshift and the prefix sum of a binary sequence are first proposed. Then, these basic operations can be used to find the kth smallest element of N m bits unsigned integers in O(m) time using N processors and to sort N data items in O(1) time using O(N^5/3) processors instead of using O(N²) processors as those proposed by other researchers

Keywords

parallel algorithms; reconfigurable architectures; CRAP; binary sequence; cross-bridge reconfigurable array of processors; interconnection scheme; parallel algorithms; Algorithm design and analysis; Binary sequences; Bridges; Checkpointing; Distributed computing; Fault tolerance; Fault tolerant systems; Parallel algorithms; Parallel processing; Very large scale integration;

fLanguage

English

Journal_Title

Parallel and Distributed Systems, IEEE Transactions on

Publisher

ieee

ISSN

1045-9219

Type

jour

DOI

10.1109/71.382325

Filename

382325