Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

Author

Sharaf, Khaled M. ; Elmasry, Mohamed I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

31

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

202

Lastpage

211

Abstract

An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented. The analytical delay model accounts for all the device parasitics and the device sizes of the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay). A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model

Keywords

bipolar logic circuits; circuit optimisation; current-mode logic; delays; emitter-coupled logic; integrated circuit modelling; logic design; analytical model; current mode logic; device parasitics; emitter-coupled logic; high-current effects; high-speed bipolar circuits; optimization; propagation delay time; series-gated CML circuits; series-gated ECL circuits; Analytical models; Circuit simulation; Design optimization; Equations; Logic circuits; Logic design; Logic devices; Propagation delay; SPICE; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.487997

Filename

487997