All-N-logic high-speed true-single-phase dynamic CMOS logic

Author

Gu, Richard X. ; Elmasry, Mohamed I.

Volume

31

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

221

Lastpage

229

Abstract

In this paper, a novel all-N-logic single-phase high speed dynamic CMOS logic is introduced and analyzed. The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks. The use of all-N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequency divider, using proposed ANL2 circuits, is simulated using 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.5 GHz. A pipelined 8-b carry generator of five-stacked NMOS transistors, which operates at a clock rate of over 710 MHz, has also been simulated. Experimental results show that the proposed circuits operate over 910 MHz implemented in a 1.2 μm CMOS technology

Keywords

CMOS logic circuits; circuit optimisation; frequency dividers; logic design; pipeline processing; 0.8 micron; 1.2 micron; 1.5 GHz; 710 MHz; 910 MHz; ANL2 circuits; all-N-logic; dynamic CMOS logic; frequency divider; high speed operation; pipelined carry generator; true-single-phase logic; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Digital signal processing; Energy consumption; Frequency conversion; MOSFETs; Pipelines; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.487999

Filename

487999