Charge Trapping Model for Temporal Threshold Voltage Shift in a-IGZO TFTs Considering Variations of Carrier Density in Channel and Electric Field in Gate Insulator

A charge trapping model is proposed considering the variations of carrier density (n_s) in the channel and electric field (F) in the gate insulator (GI) of amorphous-InGaZnO thin-film transistors (TFTs) during the gate bias stress. When the trapped electron charge amount in the GI is large enough, n_s and F decrease. These changes weaken the hopping conduction of trapped electrons in gate oxide, and hinder the electron injection into the insulator, and thus slow down TFT threshold voltage shift (ΔV_T) rate. The resulted ΔV_T model predicts accurately V_T degradation under gate bias stress, especially when the TFTs experience a long time and/or high voltage of electrical stress.