A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps

Author

Keskin, Mustafa ; Moon, Un-Ku ; Temes, Gabor C.

Author_Institution

Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

Volume

37

Issue

7

fYear

2002

fDate

7/1/2002 12:00:00 AM

Firstpage

817

Lastpage

824

Abstract

The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage ΔΣ modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35-μm CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise+distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage

Keywords

CMOS integrated circuits; circuit feedback; low-power electronics; operational amplifiers; sigma-delta modulation; switched capacitor networks; 0.35 micron; 1 V; 10 MHz; 13 bit; 20 kHz; 50 kHz; CMOS sigma-delta modulator; SNDR; dynamic range; feedback structure; low-voltage operation; pseudodifferential op amps; reset phase; signal-to-noise + distortion ratio; switched-capacitor circuits; unity-gain-reset opamps; Bandwidth; CMOS process; Clocks; Delta modulation; Dynamic range; Feedback; Signal processing; Switched capacitor circuits; Testing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.1015678

Filename

1015678