High-speed CMOS analog Viterbi detector for 4-PAM partial-response signaling

In this paper, a 1-Gb/s analog Viterbi detector based on a 4-PAM duobinary scheme is discussed with experimental results for a 0.25-μm CMOS implementation. This chip is the first analog integrated implementation of a reduced state sequence detector. Pipelining and parallel processing have been incorporated in this design for high-speed operation. Due to test equipment limitations, experimental results are given for 200-Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 55 mW from a 2.5-V supply. The active area occupies 0.78 mm². Although a duobinary scheme has been the focus of this work for its application in optical links, this design can be readily modified or extended to other partial-response signaling schemes such as dicode and PR4