Title :
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature
Author :
Liao, Yuyun ; Roberts, David B.
Author_Institution :
Intel Corp., Chandler, AZ, USA
fDate :
7/1/2002 12:00:00 AM
Abstract :
A high-performance and low-power 32-bit multiply-accumulate unit (MAC) is described in this paper. The last mixed-length encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace tree of a 12-bit encoding scheme. With this new encoding scheme, one-cycle throughput for 16-bit ×16-bit and 32-bit ×16-bit MAC instructions was achieved at very high frequencies. To handle media streams more efficiently, the single-instruction-multiple-data (SIMD) and the multiply-with-implicit-accumulate (MIA) features were added. A mixture of static CMOS logic and complementary pass-gate logic (CPL) was used to achieve the high-speed and low-power goals. Several power-saving techniques were also implemented in this MAC
Keywords :
CMOS logic circuits; coprocessors; digital signal processing chips; low-power electronics; multiplying circuits; parallel architectures; pipeline processing; reduced instruction set computing; 32 bit; complementary pass-gate logic; coprocessor; digital signal processing; four-stage Wallace tree; high throughput; high-performance; low-power; mixed-length encoding; multiply-accumulate unit; multiply-with-implicit-accumulate features; one-cycle throughput; single-instruction-multiple-data; static CMOS logic; superpipelined RISC; CMOS logic circuits; Digital signal processing; Encoding; Frequency; Microarchitecture; Microprocessors; Pipelines; Reduced instruction set computing; Streaming media; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.1015692
