Title :
Clock distribution scheme for high-speed DRAM
Author :
Kook, J. ; Wee, J.K. ; Moon, G. ; Lee, S.
Author_Institution :
Memory Res. & Dev. Div., Hynix Semicond. Inc., Kyunggi, South Korea
fDate :
6/20/2002 12:00:00 AM
Abstract :
A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results show that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage, and temperature variations
Keywords :
DRAM chips; clocks; differential amplifiers; high-speed integrated circuits; phase locked loops; poles and zeros; clock distribution scheme; clock driver; clock-skew; comparator; data buffers; differential clocking; dynamic power consumption; folded clock lines; high-speed DRAM; ideally zero-skew characteristic; low-voltage clock signals; matched resistors; phase blending circuits; pole-zero compensation; return clock; self-biased differential amplifier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020446
