Title :
An area-saving decoder structure for ROMs
Author :
Wang, Chua-Chin ; Hsueh, Ya-Hsin ; Chen, Ying-Pei
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
Read-only memories (ROMs) are widely used in both digital communication systems and daily consumer electronics. The major functions of ROMs are storage of data, programs, firmwares, etc. In this paper, a three-dimensional decoding structure for ROMs is proposed. The number of address decoding stages is drastically shortened. Hence, the delay is reduced, as well as the power consumption and area. The analysis of overall transistor count and delay is thoroughly derived. A real 256 /spl times/ 8 ROM possessing the proposed decoder is physically fabricated by 0.5-/spl mu/m two-poly two-metal (2P2M) CMOS technology.
Keywords :
CMOS memory circuits; VLSI; decoding; low-power electronics; read-only storage; 0.5 micron; ROMs; address decoding stages; area; area-saving decoder structure; digital communication systems; power consumption; three-dimensional decoding structure; two-poly two-metal CMOS technology; CMOS technology; Consumer electronics; Coupling circuits; Decoding; Delay; Digital communication; Encoding; Energy consumption; Implants; Read only memory;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2003.816134
