Title :
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
Author :
Kim, Hong-Sik ; Kim, Yongjoon ; Kang, Sungho
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
A new test-decompression methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR) is proposed. In the proposed reseeding scheme, a test cube with a large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR. The experimental results on the largest ISCAS´89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.
Keywords :
VLSI; integrated circuit testing; polynomials; sequential circuits; shift registers; system-on-chip; ISCAS´89 benchmark circuits; encoding efficiency; hardware overhead; high-rank polynomial; low-rank polynomial; reseeding scheme; test-decompression mechanism; variable-length multiple-polynomial LFSR; variable-rank MP-LFSR; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Hardware; Linear feedback shift registers; Polynomials; System testing; System-on-a-chip; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2003.812287