A systolic neural network architecture for hidden Markov models

The authors advocate a systolic neural network architecture for implementing the hidden Markov models (HMMs). A programmable systolic array is proposed which maximizes the power of VLSI implementations in terms of intensive and pipelined computing and yet circumvents the limitation on communication. A unified algorithmic formulation for recurrent back-propagation (RBP) networks and HMMs is exploited for the architectural design. It results in a basic structure for these connectionist networks that operates like a universal simulation tool, accomplishing the information storage/retrieval process by altering the pattern of connections among a large number of primitive units and/or by modifying certain weights associated with each connection. Important concerns regarding partitioning for large networks, fault tolerance for ring array architectures, scaling to avoid underflow, and architecture for locally interconnected networks are discussed. Implementations based on commercially available VLSI chips (e.g. Inmos T800) and custom VLSI technology are discussed