DocumentCode
776920
Title
Serial-parallel multiplier for two´s complement numbers
Author
Moh, S.-M. ; Yoon, S.-H.
Author_Institution
Processor Sect., Electron. & Telecommun. Res. Inst., Taejon, South Korea
Volume
31
Issue
9
fYear
1995
fDate
4/27/1995 12:00:00 AM
Firstpage
703
Lastpage
704
Abstract
A serial-parallel multiplier for two´s complement numbers is proposed. Based on an efficient two´s complement multiplication algorithm, the proposed multiplier is composed of modularised logic blocks and locally interconnected signal lines, which is suitable for VLSI implementation. It requires 2n+1 cycles to obtain a complete product, which is the same delay as in the unsigned scheme except that one XOR gate delay is added to each cycle
Keywords
VLSI; digital arithmetic; integrated logic circuits; multiplying circuits; VLSI implementation; XOR gate delay; locally interconnected signal lines; modularised logic blocks; multiplication algorithm; serial-parallel multiplier; two´s complement numbers;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19950491
Filename
384056
Link To Document