A method for detecting interconnect DSM defects in systems on chip

Author

Yang, Shih-Yu ; Papachristou, Christos A.

Author_Institution

Intel Corp., Hillsboro, OR, USA

Volume

25

Issue

1

fYear

2006

Firstpage

197

Lastpage

204

Abstract

This paper presents a built-in test method targeting interconnect defects using I_DDT testing, delay testing, and boundary scan. It was learned that I_DDT testing is an effective way to detect open and short defects. Boundary scan can provide accessibility to internal buses inside a chip. A statistical analysis method eases the uncertain factors due to process variations and power fluctuation. This paper also includes the experimental data using the proposed techniques to detect shorts, opens, or the other non-stuck-at fault type defects.

Keywords

boundary scan testing; built-in self test; integrated circuit interconnections; integrated circuit testing; statistical analysis; system-on-chip; boundary scan; built-in test method; bus interconnect testing; delay testing; interconnect DSM defects detection; internal buses; nonstuck at fault type defects; statistical analysis method; systems on chip; Circuit faults; Circuit testing; Delay; Fault detection; Integrated circuit interconnections; Power supplies; System testing; System-on-a-chip; Very large scale integration; Wires; BIST; DSM; SOC; TAP; boundary scan; bus interconnect testing; defect models;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2005.853707

Filename

1564314