The microarchitecture of the synergistic processor for a cell processor

Author

Flachs, Brian ; Asano, Shigehiro ; Dhong, Sang H. ; Hofstee, H. Peter ; Gervais, Gilles ; Kim, Roy ; Le, Tien ; Liu, Peichun ; Leenstra, Jens ; Liberty, John ; Michael, Brad ; Oh, Hwa-Joon ; Mueller, Silvia Melitta ; Takahashi, Osamu ; Hatakeyama, A. ; Wa

Author_Institution

Technol. Group, IBM Syst., Austin, TX, USA

Volume

41

Issue

1

fYear

2006

Firstpage

63

Lastpage

70

Abstract

This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.

Keywords

microprocessor chips; 11 FO4 streaming data processor; 90 nm; SOI low k process; cell processor; fine grain clock control; four way SIMD processor; instruction latency; software controls; synergistic processor microarchitecture; Application software; Bandwidth; Clocks; Computer architecture; Delay; Leakage current; Microarchitecture; Process design; Streaming media; Yarn; Cell; DSP; RISC; SIMD; SPE; SPU;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.859332

Filename

1564346