Enhanced write performance of a 64-mb phase-change random access memory

Author

Oh, Hyung-Rok ; Cho, Beak-Hyung ; Cho, Woo Yeong ; Kang, Sangbeom ; Choi, Byung-Gil ; Kim, Hye-Jin ; Kim, Ki-Sung ; Kim, Du-Eung ; Kwak, Choong-Keun ; Byun, Hyun-Geun ; Jeong, Gi-Tae ; Jeong, Hong-Sik ; Kim, Kinam

Author_Institution

SRAM Team, Samsung Electron. Co. Ltd., Gyeonggi-Do, South Korea

Volume

41

Issue

1

fYear

2006

Firstpage

122

Lastpage

126

Abstract

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-μm CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.

Keywords

CMOS memory circuits; high-speed integrated circuits; phase change materials; pulse generators; random-access storage; 0.12 micron; 1.8 V; 180 ns; 64 Mbit; 68 ns; CMOS technology; PRAM; RESET distribution; SET distribution; cell current regulator scheme; multiple step-down pulse generator; phase-change random access memory; write performance enhancement; CMOS technology; Conductivity; Crystallization; Current supplies; Low voltage; Nonvolatile memory; Phase change random access memory; Pulse generation; Random access memory; Regulators; Distribution; PRAM; RESET; phase change; set;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.859016

Filename

1564352