An Area- and Power-Efficient Compensation Technique for Voltage-Mode DACs

Although segmented voltage-mode R - 2R digital-to-analog converters (DACs) have been widely used for high-precision DACs in static applications, its code-dependent reference current induces a code-dependent IR drop through the reference and ground wires, imposing a limitation on the linearity performance. To alleviate this problem, this brief proposes a simple way to compute the reference current and compensate it via a low-resolution auxiliary DAC controlled by a computational block. A (4+12)-bit segmented voltage-mode R - 2R DAC with the proposed technique is designed and simulated in a 0.6-μm CMOS process. The SPICE simulation shows a six-time reduction of the integral nonlinearity error from the code-dependent reference current, greatly relaxing the requirement on the reference and ground distribution paths design. Compared with the conventional way of adding high-quality reference and ground buffers on chip, the proposed technique is estimated to take up 1/3 area and consume 1/5 power. With the scaling of the technology, the proposed technique becomes more competent, for 60% area comes from the purely digital computational block. Furthermore, for multichannel R - 2R DACs, the computational block can be shared among channels if time multiplexing is allowed.