• DocumentCode
    777430
  • Title

    A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

  • Author

    Kim, Kyu-hyoun ; Sohn, Young-Soo ; Kim, Chan-Kyoung ; Park, Moonsook ; Lee, Dong-Jin ; Kim, Weo-Seop ; Kim, Changhyun

  • Author_Institution
    Image Dev. Team, Samsung Electron., Gyeonggi-Do, South Korea
  • Volume
    41
  • Issue
    1
  • fYear
    2006
  • Firstpage
    127
  • Lastpage
    134
  • Abstract
    A 20-Gb/s 256-Mb DRAM with the proposed PLL and transmitter schemes has been designed and fabricated using an 80-nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with cascaded pre-emphasis transmitter achieves 10-Gb/s/pin data rate.
  • Keywords
    CMOS memory circuits; DRAM chips; cascade networks; nanotechnology; phase locked loops; phase locked oscillators; transmitters; 20 Gbit/s; 256 Mbit; 80 nm; CMOS process; DRAM; cascaded pre-emphasis transmitter; inductorless quadrature PLL; inductorless tetrahedral oscillator; inherent quadrant phases; Bandwidth; CMOS process; Circuit testing; Costs; Oscillators; Phase locked loops; Pins; Random access memory; Transmitters; Voltage; CMOSFET oscillators; DRAM chips; phase locked loops; transmitter;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2005.859017
  • Filename
    1564353
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=777430