DocumentCode :
777472
Title :
A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques
Author :
Wu, Chung-Yu ; Chen, Chih-Cheng ; Cho, Jyh-Jer
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
30
Issue :
5
fYear :
1995
fDate :
5/1/1995 12:00:00 AM
Firstpage :
522
Lastpage :
532
Abstract :
Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-μm n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 db (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm2/b, respectively
Keywords :
CMOS integrated circuits; analogue-digital conversion; current comparators; pipeline processing; 0.8 micron; 5 V; 8 bit; CMOS digital processes; analog-to-digital converter; current sample/hold amplifier; fully-differential current-mode circuit techniques; high speed differential current comparator; n-well CMOS technology; offset-canceled current comparator; one-bit-per-stage architecture; pipeline architecture; pipelined ADC; reference nonrestoring algorithm; single power supply; Analog-digital conversion; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; Capacitors; Current mode circuits; Linearity; Pipelines; Standards development;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.384165
Filename :
384165
Link To Document :
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