Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor

Author

Hart, Jason M. ; Lee, Kyung T. ; Chen, Dennis ; Cheng, Lik ; Chou, Chipai ; Dixit, Anand ; Greenley, Dale ; Gruber, Gregory ; Ho, Kenneth ; Hsu, Jesse ; Malur, Naveen G. ; Wu, John

Author_Institution

Sun Microsyst. Inc., Sunnyvale, CA, USA

Volume

41

Issue

1

fYear

2006

Firstpage

210

Lastpage

217

Abstract

This fourth-generation processor combines two enhanced third-generation cores using an advanced 90-nm dual-Vt, dual-gate-oxide technology. Hardware additions feature expanded caches and inclusion of a 2-MB Level-2 cache and a Level-3 tag. Layout was completely redrawn to optimize the design for manufacturability and performance in the latest technology. Special emphasis was placed on library development to improve automation and assist in custom design. The memory design methodologies were completely updated to make quality design simpler and more robust. The chip operates at 1.8 GHz while dissipating 90 W of power at 1.1 V.

Keywords

UHF integrated circuits; cache storage; design for manufacture; integrated circuit layout; microprocessor chips; nanoelectronics; 1.1 V; 1.8 GHz; 90 W; 90 nm; CMOS integrated circuits; SPARC V9 Microprocessor; computer architecture; custom design; design for manufacturability; dual-core microprocessor; dual-gate-oxide technology; expanded caches; fourth-generation processor; high-speed integrated circuits; integrated circuit design; library development; logic design; memory design; quality design; Design optimization; Hardware; High speed integrated circuits; History; Manufacturing; Microprocessors; Prefetching; Random access memory; Robustness; Timing; CMOS integrated circuits; computer architecture; high-speed integrated circuits; integrated circuit design; logic design; microprocessors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.859895

Filename

1564361