DocumentCode
777617
Title
A sub-10-ps multiphase sampling system using redundancy
Author
Lee, Li-Min ; Weinlader, Daniel ; Yang, Chih-Kong Ken
Author_Institution
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA
Volume
41
Issue
1
fYear
2006
Firstpage
265
Lastpage
273
Abstract
This paper demonstrates a multichannel multiphase sampling system using a 700-MHz operating frequency to produce a base sampling rate of 7 GSample/s for each channel in a typical 0.18-μm CMOS technology. An extra phase cluster with <10-ps sampling phase spacing is generated. To achieve this small phase spacing, static phase and voltage errors are digitally calibrated. Additionally, a redundancy technique is introduced in this paper to further halve the residual voltage error of the samplers. A third technique, i.e., "reference subtraction," is applied to remove cross-channel correlated dynamic noise. The resulting phase spacing is only limited by the uncorrelated random noise in the system. With this fine sampling phase resolution, this system has the ability to measure cycle-to-cycle jitter in real time.
Keywords
CMOS digital integrated circuits; clocks; jitter; random noise; redundancy; signal processing equipment; 0.18 micron; 10 ps; 700 MHz; CMOS technology; TDC; clock generation; delay-locked loops; dynamic noise; jitter; multiphase sampling system; phase spacing; random noise; redundancy technique; reference subtraction technique; residual voltage error; static phase; time-to-digital converter; CMOS process; CMOS technology; Clocks; Delay; Jitter; Phase measurement; Redundancy; Sampling methods; Testing; Timing; Clock generation; delay-locked loops (DLLs); jitter; redundancy; sampling system; time-to-digital converter (TDC);
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2005.859883
Filename
1564367
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