GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

Author

Nary, Kevin R. ; Long, Stephen I.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

Volume

27

Issue

10

fYear

1992

fDate

10/1/1992 12:00:00 AM

Firstpage

1364

Lastpage

1371

Abstract

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward

Keywords

III-V semiconductors; VLSI; direct coupled FET logic; field effect integrated circuits; gallium arsenide; integrated logic circuits; logic gates; 100 to 800 MHz; E/D mode MESFET foundry process; GaAs; NAND; NOR; NOT; TDFL gates; VLSI; low power dissipation; low-power logic family; nonoverlapping clocks; pipelined architectures; static direct-coupled FET logic; two-phase dynamic FET logic; CMOS logic circuits; FETs; Gallium arsenide; Logic design; MESFETs; Packaging; Power dissipation; Pulse inverters; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.156439

Filename

156439