Critical charge concepts for CMOS SRAMs

Author

Dodd, P.E. ; Sexton, F.W.

Author_Institution

Sandia Nat. Labs., Albuquerque, NM, USA

Volume

42

Issue

6

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1764

Lastpage

1771

Abstract

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs

Keywords

CMOS memory circuits; SRAM chips; integrated circuit modelling; integrated circuit testing; ion beam effects; ion beams; CMOS; SEU characteristics; SRAMs; critical charge concepts; external circuit loading; heavy-ion-induced charge-collection response; incident linear energy transfer; model predictions; parameter adjustments; sensitive nodes; three-dimensional mixed-mode simulations; Circuit simulation; Computational modeling; Energy exchange; Energy measurement; Laser modes; Predictive models; Random access memory; Samarium; Semiconductor device modeling; Single event upset;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.488777

Filename

488777