• DocumentCode
    777954
  • Title

    Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

  • Author

    Moreau, Yves ; Duzellier, Sophie ; Asiot, Jeang

  • Author_Institution
    Centre d´´Electron. de Montpellier, France
  • Volume
    42
  • Issue
    6
  • fYear
    1995
  • fDate
    12/1/1995 12:00:00 AM
  • Firstpage
    1789
  • Lastpage
    1796
  • Abstract
    Upsets caused by incident heavy ions on CMOS static RAMs are studied. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined
  • Keywords
    CMOS memory circuits; SRAM chips; circuit analysis computing; ion beam effects; CMOS SRAM; CMOS static RAM; charge collection mechanisms; epitaxial CMOS inverter; hit location; incidence angle; incident heavy ions; multiple bit error risk; single bit error risk; three dimensional simulation; upset risk; Circuit simulation; Electrodes; Equations; Finite element methods; Medical simulation; Packaging; Pulse generation; Random access memory; Solid modeling; Space technology;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.488780
  • Filename
    488780
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=777954