Elimination of charge-enhancement effects in GaAs FETs with a low-temperature grown GaAs buffer layer

Author

McMorrow, Dale ; Weatherford, Todd R. ; Curtice, Walter R. ; Knudson, Alvin R. ; Buchner, Steven ; Melinger, Joseph S. ; Hu Tran, Lan ; Campbell, Arthur B.

Author_Institution

Naval Res. Lab., Washington, DC, USA

Volume

42

Issue

6

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1837

Lastpage

1843

Abstract

The use of a low temperature grown GaAs (LT GaAs) buffer layer in GaAs FETs is shown via computer simulation and experimental measurement to reduce ion-induced charge collection by two to three orders of magnitude. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the FETs. Error rate calculations indicate that the soft error rate of LT GaAs integrated circuits will be reduced by several orders of magnitude when compared to conventional FET-based GaAs ICs

Keywords

III-V semiconductors; Schottky gate field effect transistors; circuit analysis computing; field effect integrated circuits; gallium arsenide; insulated gate field effect transistors; ion beam effects; radiation hardening (electronics); GaAs; GaAs FETs; GaAs integrated circuits; SEU hardening; charge-enhancement effects elimination; collected charge reduction; computer simulation; enhancement mode n-channel MESFET; error rate calculations; ion-induced charge collection; low-temperature grown GaAs buffer layer; n-channel HIGFET; soft error rate; Buffer layers; Circuits; Computer simulation; Error analysis; Extraterrestrial measurements; FETs; Gallium arsenide; MESFETs; Single event upset; Space technology;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.488787

Filename

488787