DocumentCode :
778327
Title :
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints
Author :
Potkonjak, Miodrag ; Dey, Sujit ; Roy, Rabindra K.
Author_Institution :
C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
Volume :
14
Issue :
5
fYear :
1995
fDate :
5/1/1995 12:00:00 AM
Firstpage :
531
Lastpage :
546
Abstract :
We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. The proposed approach has three components: a library of relevant transformation mechanisms, an objective function, and an optimization algorithm. The most effective transformations for testability optimization are identified by analyzing the fundamental relationship between transformational mechanisms and topological and functional properties of the computations that affect testability. A dynamic, two-stage objective function that estimates the area and testability of the final implementation, and also captures enabling and disabling effects of the transformations, is developed. Optimization is done using a new randomized branch and bound steepest descent algorithm. Application of the transformation algorithm on several benchmark examples demonstrates significant simultaneous improvement in both area and testability of the final implementations
Keywords :
boundary scan testing; circuit CAD; circuit optimisation; design for testability; high level synthesis; integrated circuit design; logic design; minimisation of switching nets; area constraints; behavioral level testability; behavioral specification; optimization algorithm; partial scan cost minimization; randomized branch/bound steepest descent algorithm; testability optimization; testable implementation synthesis; timing constraints; transformation algorithm; two-stage objective function; Automatic test pattern generation; Automatic testing; Circuit testing; Costs; High level synthesis; Process design; Sequential analysis; System testing; Throughput; Timing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.384414
Filename :
384414
Link To Document :
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