Title :
Concurrent error detection in GF(2m) multiplication and its application in elliptic curve cryptography
Author :
Chelton, W. ; Benaissa, M.
Author_Institution :
Dept. of Electron. & Electr. Eng., Sheffield Univ., Sheffield
fDate :
6/1/2008 12:00:00 AM
Abstract :
A novel approach to achieve concurrent error detection in finite-field multiplication over GF(2m) that uses multiple-bit interlaced parity codes is presented. These codes are implemented as a generic parity checker, which means they can be used with any multiplier architecture. Relative to the number of parity bits used, much improved delay and error-detection performance are achieved compared to previously reported results, yet for the examples considered the area overhead did not exceed 12%. The proposed work is particularly important for cryptography implementations employing GF(2m) multipliers and requiring reliability and protection against adversarial attacks that use fault induction.
Keywords :
cryptography; error detection codes; parity check codes; concurrent error detection; cryptography implementations; elliptic curve cryptography; error-detection performance; fault induction; finite-field multiplication; generic parity checker; multiple-bit interlaced parity codes; multiplier architecture;
Journal_Title :
Circuits, Devices & Systems, IET
DOI :
10.1049/iet-cds:20070184