• DocumentCode
    778582
  • Title

    Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers

  • Author

    Rajagopal, Sridhar ; Bhashyam, Srikrishna ; Cavallaro, Joseph R. ; Aazhang, Behnaam

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
  • Volume
    1
  • Issue
    3
  • fYear
    2002
  • fDate
    7/1/2002 12:00:00 AM
  • Firstpage
    468
  • Lastpage
    479
  • Abstract
    This paper presents algorithms and architecture designs that can meet real-time requirements of multiuser channel estimation and detection in future code-division multiple-access-based wireless base-station receivers. Sophisticated algorithms proposed to implement multiuser channel estimation and detection make their real-time implementation difficult on current digital signal processor-based receivers. A maximum-likelihood based multiuser channel estimation scheme requiring matrix inversions is redesigned from an implementation perspective for a reduced complexity, iterative scheme with a simple fixed-point very large scale integration (VLSI) architecture. A reduced-complexity, bit-streaming multiuser detection algorithm that avoids the need for multishot detection is also developed for a simple, pipelined VLSI architecture. Thus, we develop real-time solutions for multiuser channel estimation and detection for third-generation wireless systems by: (1) designing the algorithms from a fixed-point implementation perspective, without significant loss in error rate performance; (2) task partitioning; and (3) designing bit-streaming fixed-point VLSI architectures that explore pipelining, parallelism, and bit-level computations to achieve real-time with minimum area overhead
  • Keywords
    VLSI; cellular radio; code division multiple access; digital signal processing chips; fixed point arithmetic; maximum likelihood detection; multiuser channels; parallel algorithms; parallel architectures; parameter estimation; pipeline processing; radio receivers; real-time systems; bit-level computations; bit-streaming multiuser detection algorithm; code-division multiple-access; digital signal processor-based receivers; error rate performance; fixed-point VLSI architecture; fixed-point implementation; matrix inversions; maximum-likelihood estimation; minimum area overhead; multiuser channel detection; multiuser channel estimation; parallelism; pipelined VLSI architecture; real-time algorithms; real-time architecture designs; reduced complexity iterative scheme; task partitioning; third-generation wireless systems; very large scale integration; wireless base-station receivers; Algorithm design and analysis; Computer architecture; Iterative algorithms; Maximum likelihood detection; Maximum likelihood estimation; Multiuser channels; Real time systems; Signal processing; Signal processing algorithms; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Wireless Communications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1536-1276
  • Type

    jour

  • DOI
    10.1109/TWC.2002.800545
  • Filename
    1017526