Title :
An SRAM array based on a four-transistor CMOS SRAM cell
Author :
Beer, Stephan De ; Du Plessis, Monuko ; Seevinck, Evert
Author_Institution :
Dept. of Electr., Electron. & Comput. Eng., Univ. of Pretoria, South Africa
Abstract :
The static random access memory (SRAM) array discussed in this work is based on a four-transistor SRAM cell. A new method of writing the cell together with an associated array structure is proposed. The advantages are a significant reduction in power and an increase in cell reliability over previous designs. The noise margin of the cell under various conditions is investigated, as this is an effective method of designing the control mechanism of the cell.
Keywords :
CMOS memory circuits; SRAM chips; cellular arrays; integrated circuit noise; integrated circuit reliability; SRAM array; four-transistor CMOS SRAM cell; memory cell control mechanism; memory cell reliability; static noise margin; static random access memory array; voltage-deviation design; writing method; Africa; Circuits; Design methodology; Force sensors; Inverters; Logic; Monitoring; Random access memory; Threshold voltage; Writing;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
DOI :
10.1109/TCSI.2003.816316
