Title :
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
Author :
Wang, Chua-Chin ; Tseng, Yih-Long ; Lee, Po-Ming ; Lee, Rong-Chin ; Huang, Chenn-Jung
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this work, a 32-bit tree-structured carry lookahead adder (CLA) is proposed by using the modified all-N-transistor (ANT) design. The 32-bit CLA not only possesses few transistor count, but also occupies a small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 32-bit CLA can run up to 1.25 GHz at 3.3-V power supply. The output of the proposed CLA will be ready after 3.5 cycles. The proposed circuit is also easy to be expanded for long data additions. A physical chip is fabricated to verify the proposed circuit on silicon.
Keywords :
CMOS logic circuits; adders; digital arithmetic; high-speed integrated circuits; integrated circuit design; logic design; 1.25 GHz; 1P4M CMOS technology; 3.3 V; 32 bit; CLA clock; TimeMill; modified ANT logic; modified all-N-transistor design; post-layout simulation; tree-structured CLA; tree-structured carry lookahead adder; Adders; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Councils; Logic design; Power supplies; Programmable logic arrays; Silicon;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
DOI :
10.1109/TCSI.2003.816339
