High fan-in dynamic CMOS comparators with low transistor count

Author

Wang, Chua-Chin ; Lee, Po-Ming ; Wu, Chi-Feng ; Wu, Hsin-Long

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

50

Issue

9

fYear

2003

Firstpage

1216

Lastpage

1220

Abstract

In this work, we propose several high fan-in dynamic CMOS comparators with low transistor count, high speed and low power. Major features of the proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These comparators can be used as equality comparators, mutual comparators and zero/one detectors, which are widely used in built in self test and memory testing. Furthermore, a 64-bit fast dynamic CMOS comparator is implemented using the proposed dynamic comparator. The measured worst delay of the physical chip with pads is 12 ns.

Keywords

CMOS digital integrated circuits; built-in self test; comparators (circuits); high-speed integrated circuits; integrated circuit testing; low-power electronics; 12 ns; 64 bit; BIST; dynamic CMOS comparators; dynamic cell; equality comparators; high fan-in CMOS comparators; high speed comparator; low power. comparator; low transistor count design; memory testing; mutual comparators; zero/one detectors; Automatic testing; Built-in self-test; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit synthesis; Circuit testing; Delay; Detectors; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/TCSI.2003.816338

Filename

1230233