High-swing, high-drive CMOS buffer

The advent of analogue and hybrid VLSI circuits has created new requirements for the design of many previously known building blocks. For example, implementation of cascaded multilayer analogue/hybrid neural networks requires output drivers that can charge the large number of interconnecting lines, and remain stable in the presence of large capacitive loads. A CMOS high dynamic range, high-drive buffer suitable for driving large capacitive loads is presented in this paper. An area-efficient output stage has been used, with which a rail-to-rail drive capability into a 5000 pF load at 160 kHz is achieved. The circuit occupies only 110 mils² in a 3 μm technology. The output range is rail to rail for R>10 kΩ. The buffer is capable of driving resistive loads down to 300 Ω with acceptable THD