Compact low-voltage CMOS four-quadrant analogue multiplier

A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the sub-currents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 mum CMOS process are provided