DocumentCode :
780080
Title :
Modified reduced adder graph algorithm for multiplierless FIR filters
Author :
Xu, F. ; Chang, C.-H. ; Jong, C.-C.
Author_Institution :
Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
Volume :
41
Issue :
6
fYear :
2005
fDate :
3/17/2005 12:00:00 AM
Firstpage :
302
Lastpage :
303
Abstract :
A modified reduced adder graph (MRAG) algorithm and its hybrid version are proposed for efficient digital filter implementation. Several improvements are made to exploit fully the efficient optimal part of the n-dimensional reduced adder graph (RAG-n) algorithm. Simulation results demonstrate that MRAG is capable of generating lower adder cost solutions.
Keywords :
FIR filters; adders; computational complexity; graph theory; digital filter implementation; logic complexity; modified reduced adder graph algorithm; multiplierless FIR filters; n-dimensional reduced adder graph;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20057392
Filename :
1421161
Link To Document :
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