DocumentCode
780395
Title
Evaluation of a diagnosis algorithm for regular structures
Author
Caruso, Antonio ; Chessa, Stefano ; Maestrini, Piero ; Santi, Paolo
Author_Institution
Dipt. di Inf., Pisa Univ., Italy
Volume
51
Issue
7
fYear
2002
fDate
7/1/2002 12:00:00 AM
Firstpage
850
Lastpage
865
Abstract
The problem of identifying the faulty units in regularly interconnected systems is addressed. The diagnosis is based on mutual tests of units, which are adjacent in the "system graph" describing the interconnection structure. This paper evaluates an algorithm named EDARS (Efficient Diagnosis Algorithm for Regular Structures). The diagnosis provided by this algorithm is provably correct and almost complete with high probability. Diagnosis correctness is guaranteed if the cardinality of the actual fault set is below a "syndrome-dependent bound," asserted by the algorithm itself along with the diagnosis. Evaluation of EDARS relies upon extensive simulation which covered grids, hypercubes, and cube-connected cycles (CCC). Simulation experiments showed that the degree of the system graph has a strong impact over diagnosis completeness and affects the "syndrome-dependent bound," ensuring correctness. Furthermore, a comparative analysis of the performance of EDARS, with hypercubes and CCCs on one side and grids of the same size and degree on the other side, showed that diameter and bisection width of the system graph also influence the diagnosis correctness and completeness
Keywords
fault diagnosis; fault tolerant computing; graph theory; hypercube networks; multiprocessing systems; virtual machines; EDARS algorithm; cube-connected cycles; experiments; fault diagnosis; fault tolerance; faulty units; grids; hypercubes; multiprocessor systems; performance; probability; regular structure diagnosis algorithm; regularly interconnected systems; simulation; syndrome-dependent bound; system graph; wafer-scale testing; Decoding; Fault diagnosis; Hypercubes; Interconnected systems; Multiprocessing systems; Partitioning algorithms; Performance analysis; Performance evaluation; Semiconductor device modeling; System testing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2002.1017704
Filename
1017704
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